IS42S16400B-7TI(1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM For Sale

IS42S16400B-7TI(1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM


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IS42S16400B-7TI(1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM:
$4

The 64Mb SDRAM is a high speed CMOS, dynamicrandom-access memory designed to operate in 3.3Vmemory systems containing 67,108,864 bits. Internallyconfigured as a quad-bank DRAM with a synchronousinterface. Each 16,777,216-bit bank is organized as 4,096rows by 256 columns by 16 bits.The 64Mb SDRAM includes an AUTO REFRESH MODE,and a power-saving, power-down mode. All signals areregistered on the positive edge of the clock signal, CLK.All inputs and outputs are LVTTL compatible.The 64Mb SDRAM has the ability to synchronously burstdata at a high data rate with automatic column-addressgeneration, the ability to interleave between internal banksto hide precharge time and the capability to randomlychange column addresses on each clock cycle duringburst access.A self-timed row precharge initiated at the end of the burstsequence is available with the AUTO PRECHARGEfunction enabled.Precharge one bank while accessing oneof the other three banks will hide the precharge cycles andprovide seamless, high-speed, random-access operation.SDRAM read and write accesses are burst oriented startingat a selected location and continuing for a programmednumber of locations in a programmed sequence. Theregistration of an ACTIVE command begins accesses,followed by a READ or WRITE command. The ACTIVEcommand in conjunction with address bits registered areused to select the bank and row to be accessed (BA0, BA1select the bank; A0-A11 select the row). The READ orWRITE commands in conjunction with address bits reg-istered are used to select the starting column location forthe burst access.Programmable READ or WRITE burst lengths consist of1, 2, 4 and 8 locations, or full page, with a burst terminateoption

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